1. Field of the Invention
This invention relates generally to semiconductor processing and devices, and more particularly to interposer-based semiconductor chip devices, and methods of making and using the same.
2. Description of the Related Art
Stacked semiconductor chip devices present a host of design and integration challenges for scientists and engineers. Common problems include providing adequate electrical interfaces between the stacked semiconductor chips themselves and between the individual chips and some type of circuit board, such as a motherboard or semiconductor chip package substrate, to which the semiconductor chips are mounted. Still another technical challenge associated with stacked semiconductor chips is testing.
Semiconductor interposers are sometimes used to serve as a supporting and interconnect substrates for one or more semiconductor chips. A conventional semiconductor interposer consists of a silicon substrate and metallization to provide electrical pathways.
A process flow to transform bare semiconductor wafers into collections of interposers and chips and then mount the semiconductor chips on those interposers, and in-turn the interposers on circuit boards, involves a large number of individual steps. Because the processing and mounting of a semiconductor interposer proceeds in a generally linear fashion, that is, various steps are usually performed in a specific order, it is desirable to be able to identify defective parts as early in a flow as possible. In this way, defective parts may be identified so that they do not undergo needless additional processing. If, for example, the first semiconductor chip mounted to an interposer is revealed to be defective only after several other semiconductor chips are stacked thereon, then all of the material processing steps and the materials associated with the later-mounted chips may have been wasted.
Conventional interposers do not contain active devices, which might enable programming of specific identification information, such as the current processing state, the defect status, etc., of the interposers. There are conventional identification techniques, such as hard-coded metal strapping at the wafer stage and bar coding after final assembly. However, there is no ability to provide intermediary process identification information, such as defect status, customer return status, etc.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.